1. Field of the Invention
The present invention relates to a voltage regulator capable of suppressing a fluctuation in output voltage even when a power supply fluctuates.
2. Description of the Related Art
A related-art voltage regulator is described. FIG. 3 is a circuit diagram for illustrating the related-art voltage regulator.
The related-art voltage regulator includes PMOS transistors 106, 107, 108, 301, 302, and 303, NMOS transistors 103, 104, 105, 304, 305, 306, 307, and 308, resistors 109, 110, and 309, a capacitor 310, a ground terminal 100, a power supply terminal 101, and an output terminal 102.
The PMOS transistors 301, 302, and 303, the NMOS transistors 305, 306, and 308, and the resistor 309 form a bias circuit. The NMOS transistors 304 and 307 and the capacitor 310 form a control circuit. The PMOS transistors 106 and 107 and the NMOS transistors 103, 104, and 105 form an error amplifier circuit. The PMOS transistor 108 and the resistors 109 and 110 form an output circuit.
When power is supplied to the voltage regulator, a substantially uniform voltage is applied across both ends of the capacitor 310. Then, a gate voltage of the NMOS transistor 304 is raised to a power supply voltage VDD, thereby turning on the NMOS transistor 304, with the result that a gate voltage of the PMOS transistor 303 is decreased to a ground voltage. Thus, the PMOS transistor 303 is turned on to increase a gate voltage of the NMOS transistor 103. As a result, a current flowing through the NMOS transistor 103 is increased, and hence an operating speed of the error amplifier circuit is temporarily increased. In this way, overshoot and undershoot, which may occur due to a low operating speed of the error amplifier circuit, are prevented, thereby being capable of preventing adverse effects on a circuit connected downstream of the output terminal 102.
Then, as the capacitor 310 is charged, the gate voltage of the NMOS transistor 304 is decreased. When the gate voltage is decreased to be a threshold Vth or less, the NMOS transistor 304 is turned off. Thus, the entire operation of the control circuit is stopped. At this time, the power supply voltage VDD is in a steady state, and hence the voltage regulator normally operates.
After that, if the power supply voltage VDD suddenly changes, the following operation is performed to prevent overshoot and undershoot as in the case described above. Specifically, when the power supply voltage VDD is first decreased, charges of the capacitor 310 are discharged, and when the power supply voltage VDD is next increased, an operating current of the error amplifier circuit is increased through operation similar to that described above (for example, see Japanese Patent Application Laid-open No. 2001-22455).
However, the related-art voltage regulator has the following problems. One problem is that the gate voltage of the PMOS transistor 303 varies even when the power supply voltage VDD slightly fluctuates, and hence a tail current of the error amplifier circuit is frequently changed to change an operating point of the error amplifier circuit, with the result that the operation of the voltage regulator is unstable. Another problem is that when the power supply voltage VDD largely fluctuates, a current of the PMOS transistor 303 is unlimitedly increased to excessively increase the tail current of the error amplifier circuit, with the result that the operation of the voltage regulator is unstable.